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PD - 94523
IRFR3518 IRFU3518
Applications l High frequency DC-DC converters
HEXFET(R) Power MOSFET
VDSS
80V
RDS(on) max
29mW
ID
30A
Benefits l Low Gate-to-Drain Charge to Reduce Switching Losses l Fully Characterized Capacitance Including Effective COSS to Simplify Design, (See App. Note AN1001) l Fully Characterized Avalanche Voltage and Current
D-Pak IRFR3518
I-Pak IRFU3518
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C dv/dt TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
80 20 38 27 150 110 0.71 5.2 -55 to + 175 300 (1.6mm from case )
Units
V
A W W/C V/ns C
Thermal Resistance
Parameter
RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB mount) Junction-to-Ambient
Typ.
--- --- ---
Max.
1.4 40 110
Units
C/W
Notes through are on page 10
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1
09/23/02
IRFR3518/IRFU3518
Static @ TJ = 25C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) Gate Threshold Voltage V(BR)DSS IDSS IGSS Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. 80 --- --- 2.0 --- --- --- --- Typ. --- 0.09 24 --- --- --- --- --- Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 29 m VGS = 10V, ID = 18A 4.0 V VDS = VGS, ID = 250A 20 VDS = 80V, VGS = 0V A 250 VDS = 64V, VGS = 0V, TJ = 150C 200 VGS = 20V nA -200 VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. 34 --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. --- 37 11 12 12 25 37 13 1710 270 33 1780 170 330 Max. Units Conditions --- S VDS = 25V, ID = 18A 56 ID = 18A --- nC VDS = 40V --- VGS = 10V --- VDD = 40V --- ID = 18A ns --- RG = 9.1 --- VGS = 10V --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 64V, = 1.0MHz --- VGS = 0V, VDS = 0V to 64V
Avalanche Characteristics
Parameter
EAS IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Typ.
--- --- ---
Max.
160 18 11
Units
mJ A mJ
Diode Characteristics
IS
ISM
VSD trr Q rr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol 38 --- --- showing the A G integral reverse --- --- 150 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 18A, VGS = 0V --- 77 --- ns TJ = 25C, IF = 18A --- 210 --- nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFR3518/IRFU3518
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
1000
TOP
100
100
I D, Drain-to-Source Current (A)
BOTTOM
I D, Drain-to-Source Current (A)
BOTTOM
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
10
10
4.5V
1
4.5V
1
0.1
20s PULSE WIDTH T J= 25 C
0.01 0.1 1 10 100
20s PULSE WIDTH T J= 175 C
0.1 0.1 1 10 100
V DS Drain-to-Source Voltage (V) ,
V DS Drain-to-Source Voltage (V) ,
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.00
3.0
I D = 38A
ID, Drain-to-Source Current ()
2.5
100.00
RDS(on) , Drain-to-Source On Resistance
T J = 25C T J = 175C
2.0
(Normalized)
1.5
10.00
1.0
VDS = 25V 20s PULSE WIDTH
1.00 4.0 6.0 8.0 10.0 12.0 14.0 16.0
0.5
V GS = 10V
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V)
Tj, Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRFR3518/IRFU3518
100000 VGS = 0V, f = 1 MHZ Ciss = C + C , C SHORTED gs gd ds Crss = C gd Coss = C + C ds gd
12
VGS, Gate-to-Source Voltage (V)
ID = 18A VDS= 40V VDS= 64V VDS= 16V
10 8 6 4 2 0
10000
C, Capacitance(pF)
C iss
1000
C oss
100
C rss
10 1 10 100
0
10
20
30
40
VDS, Drain-to-Source Voltage (V)
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000 OPERATION IN THIS AREA LIMITED BY R DS(on)
100
TJ = 175 C
10
ID, Drain-to-Source Current (A)
100
I SD , Reverse Drain Current (A)
10
100sec 1msec
T J= 25 C
1
1 Tc = 25C Tj = 175C Single Pulse 0.1 1 10 10msec
V GS = 0 V
0.1 0.0 0.5 1.0 1.5 2.0
V SD ,Source-to-Drain Voltage (V)
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFR3518/IRFU3518
40
V DS
LIMITED BY PACKAGE
RD
VGS
30
RG VGS
D.U.T.
+
-VDD
I D , Drain Current (A)
20
Pulse Width 1 s Duty Factor 0.1 %
Fig 10a. Switching Time Test Circuit
10
VDS 90%
0 25 50 75 100 125 150 175
TC , Case Temperature ( C)
10% VGS
td(on) tr t d(off) tf
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10b. Switching Time Waveforms
10
(Z thJC )
1 D = 0.50
Thermal Response
0.20 0.10 0.1 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = 2. Peak T 0.01 0.00001 0.0001 0.001 0.01 t1/ t
2
P DM
J = P DM x Z thJC
+T C 1
0.1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR3518/IRFU3518
15V
320
TOP
RG
20V
D.U.T
IAS tp
+ V - DD
A
EAS , Single Pulse Avalanche Energy (mJ)
VDS
L
DRIVER
240
BOTTOM
ID 7.3A 13A 18A
160
0.01
Fig 12a. Unclamped Inductive Test Circuit
80
V(BR)DSS tp
0 25 50 75 100 125 150 175
Starting Tj, Junction Temperature
( C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
QG
12V .2F
50K .3F
QGS VG
QGD
D.U.T. VGS
3mA
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRFR3518/IRFU3518
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET(R) Power MOSFETs
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7
IRFR3518/IRFU3518
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 1.27 (.050) 0.88 (.035)
2.38 (.094) 2.19 (.086)
1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018)
6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 3 0.51 (.020) MIN. 10.42 (.410) 9.40 (.370) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN -B1.52 (.060) 1.15 (.045) 3X 2X 1.14 (.045) 0.76 (.030) 0.89 (.035) 0.64 (.025) 0.25 (.010) M AMB NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 4.57 (.180) 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006).
0.58 (.023) 0.46 (.018)
2.28 (.090)
D-Pak (TO-252AA) Part Marking Information
8
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IRFR3518/IRFU3518
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 1.27 (.050) 0.88 (.035)
2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN
6.45 (.245) 5.68 (.224) 1.52 (.060) 1.15 (.045) 1 -B2.28 (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) 2 3 6.22 (.245) 5.97 (.235)
NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006).
3X
1.14 (.045) 0.76 (.030)
3X
0.89 (.035) 0.64 (.025) M AMB
1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018)
2.28 (.090) 2X
0.25 (.010)
I-Pak (TO-251AA) Part Marking Information
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9
IRFR3518/IRFU3518
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL
16.3 ( .641 ) 15.7 ( .619 )
16.3 ( .641 ) 15.7 ( .619 )
12.1 ( .476 ) 11.9 ( .469 )
FEED DIRECTION
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. Starting TJ = 25C, L = 0.99mH R G = 25, IAS = 18A. ISD 18A, di/dt 360A/s, VDD V(BR)DSS, TJ 175C. Pulse width 300s; duty cycle 2%.
Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 09/02
10
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